module sumator_complet_1bit (Cout, out, A, B, Cin); input A, B, Cin; output Cout, out; assign {Cout, out} = A + B + Cin; endmodule module teste_sumator_complet_1bit; reg A, B, Cin; wire Cout, out; initial begin A = 0; B = 0; Cin = 0; #10 A = 0; B = 0; Cin = 0; #10 A = 0; B = 0; Cin = 1; #10 A = 0; B = 1; Cin = 0; #10 A = 0; B = 1; Cin = 1; #10 A = 1; B = 0; Cin = 0; #10 A = 1; B = 0; Cin = 1; #10 A = 1; B = 1; Cin = 0; #10 A = 1; B = 1; Cin = 1; end sumator_complet_1bit instanta(Cout, out, A, B, Cin); endmodule ----------------------------sumator 4 biti----------------- module sumator_4biti(Cout, out, A, B, Cin); input[3:0] A, B; input Cin; output[3:0] out; output Cout; reg[3:0] out; reg Cout; always @(A or B or Cin) //{Cout, out} <= A + B +Cin; if(A + B + Cin <= 15) begin out <= A + B + Cin; Cout <= 0; end else begin out <= A + B + Cin; Cout <= 1; end endmodule module test_sumator_4biti; reg[3:0] A, B; reg Cin; wire[3:0] out; wire Cout; initial begin A = 0; B = 0; Cin = 0; #10 A = 0; B = 0; Cin = 0; #10 A = 1; B = 0; Cin = 0; #10 A = 1; B = 1; Cin = 0; #10 A = 1; B = 1; Cin = 1; #10 A = 3; B = 3; Cin = 0; #10 A = 3; B = 3; Cin = 1; #10 A = 14; B = 1; Cin = 0; #10 A = 14; B = 1; Cin = 1; #10 A = 15; B = 15; Cin = 0; #10 A = 15; B = 15; Cin = 1; end sumator_4biti instanta(Cout, out, A, B, Cin); endmodule

module mux(out,sel,in0,in1,in2,in3); input [3:0]in0,in1,in2,in3; input [1:0]sel; output reg[3:0]out; always@(sel) begin case(sel) 0: out=in0; 1: out=in1; 2: out=in2; 3: out=in3; default: $display("Verifica functia!"); endcase end endmodule module test_mux(); reg [3:0]in0,in1,in2,in3; reg [1:0]sel; wire [3:0]out; initial begin sel=0;in0=0;in1=1;in2=2;in3=3; #10 sel=1; end mux instanta (out,sel,in0,in1,in2,in3); endmodule

module sumator_complet_1bit (Cout, out, A, B, Cin); input A, B, Cin; output Cout, out; assign {Cout, out} = A + B + Cin; endmodule module teste_sumator_complet_1bit; reg A, B, Cin; wire Cout, out; initial begin A = 0; B = 0; Cin = 0; #10 A = 0; B = 0; Cin = 0; #10 A = 0; B = 0; Cin = 1; #10 A = 0; B = 1; Cin = 0; #10 A = 0; B = 1; Cin = 1; #10 A = 1; B = 0; Cin = 0; #10 A = 1; B = 0; Cin = 1; #10 A = 1; B = 1; Cin = 0; #10 A = 1; B = 1; Cin = 1; end sumator_complet_1bit instanta(Cout, out, A, B, Cin); endmodule ----------codificator------------- module codificator(C, I); input[7:0] I; output reg[2:0] C; always @(I) begin C[0] = I[1] | I[3] | I[5] | I[7]; C[1] = I[2] | I[3] | I[6] | I[7]; C[2] = I[4] | I[5] | I[6] | I[7]; end endmodule module test_codificator; reg[7:0] I; wire[2:0] C; initial begin I=0; #10 I=1; #10 I=2; #10 I=4; #10 I=8; #10 I=16; #10 I=32; #10 I=64; #10 I=128; end codificator instanta(C, I); endmodule