module mux(out,sel,in0,in1,in2,in3); input [3:0]in0,in1,in2,in3; input [1:0]sel; output reg[3:0]out; always@(sel) begin case(sel) 0: out=in0; 1: out=in1; 2: out=in2; 3: out=in3; default: $display("Verifica functia!"); endcase end endmodule module test_mux(); reg [3:0]in0,in1,in2,in3; reg [1:0]sel; wire [3:0]out; initial begin sel=0;in0=0;in1=1;in2=2;in3=3; #10 sel=1; end mux instanta (out,sel,in0,in1,in2,in3); endmodule